The present invention relates to integrated circuit design, and more specifically, to clock network analysis using harmonic balance.
Integrated circuit design or chip design, as it is commonly known, involves multiple tasks that are performed at different phases to develop a logical design into a physical implementation of the chip. One of the tasks is analysis of the on-chip clock network which examines how and when a clock signal reaches each location or node in the chip. The analysis yields a clock signal waveform at each node. The clock signal waveforms provide values of interest in clock network analysis such as, for example, timing, overshoot, and undershoot. Two different clock network architectures are clock trees and clock grids. In a clock tree, the branches are unrelated such that leaves of different branches experience different clock delays. In a clock grid, metal wires connect the endpoints of each of the clock signal paths. As such, the clock skew, or the maximum difference among delays at the endpoints, is small. The coupling among the different clock paths in a clock grid makes clock network analysis different for the clock grid architecture than for the clock tree architecture.